The invention relates to telecommunication products and more particularly to a switching system including a mask mechanism for altering the internal routing process of a switching system.
The invention is an improvement to prior art switching systems employing a shared buffer, and particularly to a system disclosed in European patent applications no 97480057.5, 97480056.7, 97480065.8, 96480129.4, 96480120.3 assigned to the assignee of the present application.
Shared buffer switching is very useful for routing small cells of data such as ATM cells having a limited number of bytes; generally 53 bytes. The high transmission rates that are needed today thus require the switching of a great number of data cells. The switching process is however limited by the physical storage capacity of the buffer, where the cells are stored prior to their routing to the appropriate port destinations. In case of multicasting (nearly simultaneous distribution of the same cell to multiple destinations) a cell occupies its location within the shared buffer as long as the duplication operations required for multicasting are still pending, which takes a relatively long time when a contention occurs in one port of the switch. In the system described in the above mentioned European applications, the shared buffer has 128 locations used for the storage of the cells prior to their routing towards the appropriate output ports.
It is highly desirable to expand the capability of the switching architecture by possibly allowing the combination of elementary switching modules. The above mentioned European applications describe speed expansion, and port expansion architectures which respectively allow the expansion of the switching rate and the number of ports of the switching architecture. By doubling the number of switching modules by two it is possible to double the speed of the switch. Using four modules in combination makes it possible to double the number of ports of the switch.
However, in these situations, the buffer remains limited to 128 storage locations which inevitably limits the possibilities of the switch and increases the risks of contention.
It is an object of the present invention to provide a switching architecture that can benefit from the individual storage resources of first and second switching systems in order to expand the capabilities of the switch.
It is another object of the present invention to provide a shared buffer switching architecture which supports speed expansion, port expansion and buffer expansion.
It is a further object of the present invention to provide a switching architecture that can aggregate individual switching systems in order to enhance the switching performance.
These and other objects are achieved by a switching system including a set of input port adapters on which cells may be received, each cell carrying a bitmap value, and a set of output port adapters to which cells may be routed. The system further includes a mask register for altering the value of the bitmap and a module for performing a cell routing process. The module includes a shared buffer for temporarily storing cells which are received and logic for controlling the routing of each cell as a function of the bitmap value produced by the mask mechanism.